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Performance Comparison of Adaptalog's LDO Bandgap Circuits with Standard LDO Bandgap Arrangements

Flatband Noise Normalised Flicker Noise Beta Sensitivity RBase Sensitivity Additional Information
Circuit (link) (nV/rtHz)
50-uA
27°C
dB
Rel. Brokaw
mV pk-pk
25<beta<
noise gain
dB
Widlar pair 42.6
42.3
-7.2
-17
28
20.2
12.1
12.1
Unbuffered base
Buffered base
Prior Art.
Notes: 1, 3
Widlar-
Frederiksen
40.5
38.4
-17
-0.5

0.47
4

12.1
12.1
Optimum beta sensitivity
Optimum flatband noise
Prior Art.
Notes: 1, 3
Brokaw 46.3 0
(reference)
1.0 11.9   Prior Art.
Notes: 1, 3
Dual-sense 37.2
33.5
33.2
-17.9
-5.3
-2.8
18
0.81
5.7
12.8
12.8
12.8
Optimum flicker noise
Optimum beta sensitivity
Optimum flatband noise
Adaptalog IP.
Notes: 1, 2, 3, 5
Recursive "Brokaw" 30.3 -9.2 29 10.1

(High impedance output,
and >300-mV drop-out)

Adaptalog IP.
Note: 1
Recursive
Dual-sense
27.6
26.5
-17
-8.3
15.1
2.3
10.1
10.1
Optimum flicker noise
Optimum flatband noise
Adaptalog IP.
Notes: 1, 2, 5
>300-mV drop-out
Recursive
Dual-sense + spacer
18.8
18.8
18.8
-20
-15.8
-18.8
5.3
0.53
3.0
8.9
8.9
8.9
Optimum flicker noise
Optimum beta sensitivity
Optimum flatband noise
Adaptalog IP.
Notes: 1, 2, 5
CMOS compatible 20.3 - 25 <-22 0.08 6.1 Flatband noise level is
process dependent
Adaptalog IP.
Notes: 1, 3, 4, 5
Optim 11.8
11.8
-16.8
-14.9
2.1
0.11
6.1
6.1
Optimum flicker noise
Optimum beta sensitivity
Adaptalog IP.
Notes: 1, 3, 4, 5

Note 1
a) Bandgap cells in all designs would fit into similar areas (< 0.02-sq.mm. in a 0.6-um process)
b) Values are simulated for 60-uA ground current and 27 OC operating temperature
c) All performance parameters relate to nominal transistors (RB=0 beta=100, NF=1, etc.) except beta sensitivity and base noise gain
d) All circuits provide the same reference/regulator Voltage, and use identical transistor models
e) In the Widlar pair, the difference between the bandgap Voltage and the forward Voltage of the single-area transistor is 0.5 Volts
Note 2   
Further improvements may be possible, as the variables have not yet been independently optimised.
Note 3
Suitable for processes that provide only a single-polarity of bipolar transistor
Note 4
Schematics for these circuit arrangements will be released at a later date
Note 5
Significant additional reductions in noise levels are possible when the regulator does not need to provide a low drop-out Voltage